The present invention, generally, relates to data processing systems and, more particularly, to an interconnection arrangement for a plurality of data processing systems.
As used herein, a "microprocessor" circuit is a small electronic chip that is capable of performing a multitude of computer functions reliably and efficiently. Such a microprocessor chip may be used for the data processor, described hereinafter.
It is recognized that, even though a present-day microprocessor circuit is capable of performing assigned tasks faster than even much larger computers of a few years ago, there are instances in the process controls industry, the simulator industry, and in many other industries when still more performance is needed. In the past, connecting two or more of such microprocessor circuits together has provided the needed additional data processing power.
However, as the number of such interconnected microprocessors has grown, the overall processing power has not grown proportionately. Whereas two microprocessors might give twice the processing power of one microprocessor, ten microprocessors connected together might give only seven times the processing power of one microprocessor.
The reason for this degradation is that usually the individual microprocessor circuits must communicate data between one another, and a substantial amount of time is lost in doing this. In one arrangement, the microprocessors send messages across a group of wires, known as a "bus". Control signals, however, must be exchanged first on this bus, to signal that, for instance, microprocessor A has a message for microprocessor E, that microprocessor E is now ready to receive the message, that the message is now on certain other wires of the bus, that the message has been received, and so on. In most such arrangements, this exchange of control signals must occur for each character, or computer "word", of information to be passed.
In another arrangement, all microprocessors have access through a common bus to a common memory, in which all information or data required by any of the microprocessors is placed. The microprocessors must then send signals across the bus requesting permission to write data into the memory or to read data out. In the process, they often contend for the bus (and for the memory) at the same instant, and one must wait for the other, often by means of a complex priority arbitration scheme and circuitry.
Many other arrangements are possible, including one in which each microprocessor has a certain amount of private memory in addition to the common memory. In such arrangements, any data that is used only by one microprocessor is kept in the private memory of that microprocessor, and only data that is needed by two or more microprocessors is placed in the common memory.
Often it is found, however, that even with this arrangement, when enough microprocessors are added to the bus, some microprocessors will be completely prevented from attaining access to the common memory. When this happens, the overall computing task cannot be completed.
In part, this effect stems from the random timing of the requests for access to the bus and to the common memory acting in concert with the priority arbitration circuits. In situations where the random timing of requests can be replaced by a fixed schedule of requests, a design often can be set up in which all required accesses have defined time slots and will be attained.
This arrangement, however, would normally require that the programs for all microprocessors be developed and synchronized carefully so that each microprocessor made its request at precisely the right instant. If the requests are scattered throughout each program, this places a very difficult burden on the program, and synchronization is difficult or impossible to retain when the design of the program, for other reasons, must change.
A variation of this arrangement establishes a series of time frames in which computing by all microprocessors occurs, separated by periods in which substantially no computing occurs, but data transfers to and from the common memory occur. Such a system can be used by processes in which a periodic exchange of data is consistent with the computation being performed, a condition which does exist in the simulation industry or in other industries.
When program changes occur, however, and especially when those program changes require different accesses to the common memory, then all or most of the programs for the various microprocessors that perform the data interchange must be changed also, because a change in one part of the interchange schedule affects all other parts. This destroys a very desirable property of the programs for the various microprocessors, that is, their independence from changes in other microprocessors.
This independence can be restored through the use of this invention. Each microprocessor is provided with a private memory, and there is also a common memory. However, all of the microprocessors do not access the common memory directly, and the program for these microprocessors need not concern themselves with the data interchange.
A separate microprocessor is dedicated to accomplishing all of the data interchange; it is called the "data transfer controller". The data transfer occurs over a special data transfer bus, which connects to each of the private memories through a second port on each of these memories, that is, a separate port from the one by which the individual microprocessor accesses that private memory.
Data transfers on this special data transfer bus are always either from a private memory to the common memory or from the common memory to a private memory. These transfers are initiated and controlled by the data transfer controller.
In one embodiment, the common memory is, in effect, a private memory of the data transfer controller; the data transfer controller accesses the special data transfer bus directly to all the private memories, reading or writing one or another of those memories. As it reads data from one of the private memories, it places that data in a known location in its own private memory, that is, actually the common memory. Later, that data will be read from the common memory by the data transfer controller and written into one or more of the private memories.
The data transfer controller directs this data transfer on a fixed time schedule, which is synchronized with the programs in the various microprocessors by a common clock circuit which interrupts all microprocessors, including the data transfer controller, at regular intervals. In this way the data transfer controller can initiate transfer at times when the transfer will not impact the computations in the individual microprocessors.
In another embodiment, the common memory is connected also to the special data transfer bus. Data in this case also is transferred only from one of the private memories to the common memory or from the common memory to one of the private memories, but in this case, the transfer may occur in blocks under the control of what is commonly known in the art as a Direct Memory Access (DMA) circuit.
The role of the data transfer controller in this embodiment is to perform the setup of the DMA circuit, that is, to instruct the DMA circuit as to the starting addresses of a block of data (in both the private memory and the common memory) and the length of the block of data. Then, the data transfer controller instructs the DMA circuit to begin transferring data.
In both cases, the schedule by which information is moved about the system is built into the program for the data transfer controller, and the schedule does not appear in any of the programs for the individual microprocessors. In the event that a change in the schedule of data transfer is required, only the program in the data transfer controller need be changed.
It is usual in the simulator industry, and in other industries, to provide support programs and data bases which operate offline (that is, which do not operate directly as part of the group of microprocessors considered here). In certain of these support programs and data bases, knowledge is maintained of the data variables produced in each of the individual microprocessors and the data variables required by each of the individual microprocessors.
With this knowledge, these offline programs can develop, essentially automatically, the computer program needed for the data transfer controller. Any program changes involving data transfer in the individual microprocessors would be reflected in the offline data base, and upon running the offline support program, a new data transfer program would result for the data transfer controller.